Frequency dividers are often used in integrated circuits to divide the frequency of an incoming clock signal down to a required frequency. FIG. 1, for example, is a schematic diagram illustrating a conventional divider 100. As illustrated, the divider 100 comprises a high speed divider 102 and a low speed divider 106. The high speed divider 102 divides the frequency of an incoming clock signal by a fixed amount N. The divided clock signal is then passed to the low speed divider 106 for further division by a programmable amount P. A final divided-down clock (divided by N*P) is then output by the low speed divider 106.
The divider ratios that are achievable using the divider 100 are limited by the capabilities of the high speed divider 102. Specifically, achievable divider ratios comprise the high speed divider ratio (which is fixed at N) multiplied by the low speed divider ratio (which is programmable up to P). Thus, only divider ratios that are multiples of N (e.g., 1N, 2N, . . . , PN) are achievable; divider ratios that are not multiples of N (which includes most prime numbers, among others) are not supported. Thus, although the divider 100 affords some programmability in divide ratio, this programmability is limited.
In addition, increased programmability in divide ratio often limits high-speed design robustness. For example, programmability tends to cause additional timing delays during control, which consumes the overall timing budget and sets a high-speed design limit. Thus, conventional dividers tend to be either highly programmable or highly high-speed robust, but not both.